The present invention relates to the design of an integrated circuit chip that supports through-chip communication.
Conductive electrical interconnections and transceivers have long being used to provide reliable interconnections to and from semiconductor devices, and have dominated the interconnect hierarchy because of significant advantages in packaging and manufacturing. As decreasing linewidths allow millions of circuit elements to be incorporated into a semiconductor chip, and as these circuit elements are able to operate at faster on-chip clock rates, traditional resistive wires are no longer able to provide the off-chip bandwidths necessary to fully utilize the computational resources available on-chip.
For performance and scalability reasons, “conventional” current-modulation or current-injection Vertical Cavity Surface Emitting Lasers (VCSELs) are bandwidth limited for the following reasons: (1) they have topological limits which are typically related to perimeter wiring (wire-bonds) or low-density 2-dimensional area array flip-chip bonding; (2) they have RC limits which are caused by charging and discharging of contact and parasitic capacitance; and (3) there is lower power dissipation for off-chip drivers which must drive low-impedance lines.
To overcome these inherent limitations, a new form of inter-chip or inter-wafer signaling, called “proximity communication,” has recently been proposed (see I. Sutherland, “Face-to-Face Chips,” U.S. Pat. No. 6,500,696, issued Dec. 31, 2002). This communication technique relies on capacitive coupling between chips which are oriented face-to-face. Capacitive coupling allows signal densities two orders of magnitude greater than traditional off-chip communication using wire-bonding or traditional ball-bonding. Additionally, the associated circuits and coupling structures are fully compatible with the standard CMOS foundries with no modifications needed to their processes. Furthermore, in order to communicate off-chip, the circuits typically drive a high-impedance, capacitive pad, very much akin to the gate of a transistor. This eliminates the need for high-to-low impedance conversion, which has traditionally prevented substantive reduction in the power dissipation of the off-chip driver circuits in spite of improvements in transistor efficiency.
Ultimately, proximity communication provides an off-chip signaling bandwidth that can scale with the feature size and on-chip frequency. However, a number of topological constraints have been required to make this form of communication to be effective. As illustrated in FIG. 1 and FIG. 2, the chips needed to face each other, with their active sides abutting with full or partial overlap. As shown in FIG. 2, this allows for a two-layer stack of chips to be formed and scaled in planar configurations.
Furthermore, optical interconnections and transceivers are now also being used to provide reliable interconnections between electronic components. These can scale in both distance and speed. As one example, optical links based on VCSELs have had a substantial impact into this industry as a low-cost, wafer-scale, and high-speed device that can directly be driven by low-cost silicon circuits for transceivers in the 1-10 Gbit/s range.
Recently, it has also been shown that such VCSELs and other optoelectronic components, including detectors and optical modulators, can be directly integrated with Silicon CMOS (see A. Krishnamoorthy, and K. W. Goossen, “Optoelectronic-VLSI: Photonics integrated with VLSI circuits,” IEEE J. Special Topics in Quantum Electronics, Vol. 4, No. 6, pp. 899-912, January 1999). It has also been shown that both top-emitting as well as bottom-emitting VCSELs configurations can be used for this integration.
A straightforward combination of capacitive coupling and optical signaling is illustrated in FIG. 3. Chips are placed face-to-face allowing planar tiling with both optical and capacitive coupling of signals to the active surface of the chips, namely the side that is processed with transistor circuits, various metallizations and optical devices respectively.
For topological reasons, there is a potential advantage in a more generalized structure wherein chips may be stacked in three dimensions. Additionally, for packaging and heat-removal reasons, it may be advantageous even for a two-chip stack for the active surfaces of both chips to face the same direction. By contrast, conductive communication through a chip suffers from a need to fabricate a conductive “via” through the chip. Thus, there is a need for a form of two-sided wireless chip or wafer communication without the limitations of the aforementioned art.